Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults

Testing for small-delay defects (SDDs) has become necessary as technology further scales. Existing tools and methodologies for generating SDD patterns suffer from: limited long-paths sensitization capability, overwhelming pattern volume, time-consuming pattern generation process, and vague evaluations of pattern quality. Such situation places patterns in a dilemma where the generation and application effort are huge yet the results cannot Responsible Editor: C. Metra The original verision of this paper was presented at the 16th European Test Symposium, May 23–27, 2011, Trondheim, Norway. The work of F. Bao, K. Peng and M. Tehranipoor was supported in part by NSF under Grants no. ECCS-0823992 and CCF-0811632. The work of K. Chakrabarty was supported in part by SRC under Contract No. 1588 and by NSF under Grant no. ECCS-0823835. F. Bao ( ) · M. Tehranipoor ECE Department, University of Connecticut, 115 North Eagleville Road, Storrs-Mansfield, CT 06269, USA e-mail: [email protected] M. Tehranipoor e-mail: [email protected] K. Peng · L. Winemberg Freescale Semiconductor, 6501 William Cannon W Dr, Austin, TX 78735, USA M. Yilmaz Nvidia Corporation, 2701 San Tomas Expressway #01, Santa Clara, CA 95050, USA K. Chakrabarty ECE Department, Duke University, Durham, NC 27708, USA e-mail: [email protected] reflect the physical phenomena clearly enough for correct binning and diagnosis. In this paper, we focus on establishing a pattern generation flow that produces patterns of high application value. Firstly, critical faults are identified in order to generate high-quality original pattern repository with n-detect ATPG.A novel pattern evaluation and selection method that further minimizes pattern count while maintaining the SDD detection ability is then presented. Top-off ATPG is then performed to ensure meeting the target fault coverage. Along with the flow, multiple evaluation metrics are also proposed to measure the pattern’s efficiency on SDD coverage, unique SDD detection, detectable SDD size, long path distribution, etc. Experimental results demonstrate that the proposed critical fault-based method improves long path sensitization efficiency by 2.5× without impairing its average delay and saves approximately 80 % CPU runtime compared with total fault-based method. Comparing with timing-aware ATPG, the generated pattern set detects equivalent or even more SDDs with significantly reduced pattern count.